AMIS-53000 Datasheet, PDF (46/99 Pages) AMI SEMICONDUCTOR – Frequency Agile Transceiver

AMIS-53000 Frequency Agile Transceiver
Data Sheet
Setup registers descriptions:
Status- Contains the results of calibrations, instructions and activity in the AMIS-53000.
Software State- Shows the current mode of the AMIS-53000.
6.4.5.1. Status/Flag1
The purpose of the Status1 register is to provide information back to the host on the status of the part. This register should be queried
at the completion of calibration sequences to ensure proper operation. The flags will be reset when the register is read.
CheckSum indicates whether an attempt to read or write the EE has failed due to an incorrect CheckSum.
Instruction enable indicates that the AMIS-53000 is ready to receive an instruction. This can be used to insure that the AMIS-53000
does not miss a command instruction due to the AMIS-53000 not being ready. Along with the busy flag, these status flags can police
the flow of commands to the AMIS-53000.
Table 29: Status/Flag1 - 0X01 [1]
Bit Name
State
1
7
PLL xLock
0
1
6
TX PLL Cal
0
1
5
RX PLL Cal
0
1
4
RC Cal
0
1
3
Quick Start Cal
0
1
2
CheckSum
0
1
1
Instruction Enable
0
1
0
ADC Done
0
Comment
PLL out of lock on startup (RX, TX, Sniff, Burst)
PLL calibration for transmit failed
PLL calibration for receive failed
10kHz RC oscillator calibration failed
Quick Start calibration failed
EE CheckSum failed
The AMIS-53000 is in a state of operation that can accept instructions
ADC conversion complete
6.4.5.2. Status/Flag2
The Status2 register provides information on the operating status of the part. The busy bit is asserted for any of the following reasons:
Calibration: The busy bit will remain high for the duration of a calibration sequence. Status2 can be repeatedly polled during
a calibration sequence to determine when it’s complete.
Read/Write EE: While the AMIS-53000 is reading from or writing to the EE, the busy bit will remain set.
Buffered RX: When in receive mode, and a valid chip ID is found, the AMIS-53000 will begin processing of this packet.
During the time the packet is being processed, the busy bit will be set high.
Buffered TX: After the command is given for transmit with the buffered packet option enabled, the busy bit will remain high
until the part has completed the actual transmission of the packet.
Housekeeping: Busy is asserted during a housekeeping cycle.
Burst TX: Busy is asserted during a Burst transmission.
AMI Semiconductor – Aug. 05, Rev. 1.0
46
www.amis.com