AMIS-53000 Datasheet, PDF (32/99 Pages) AMI SEMICONDUCTOR – Frequency Agile Transceiver

AMIS-53000 Frequency Agile Transceiver
Data Sheet
Figure 25 shows a single read or single write control data transfer. The operation starts with SSN transitioning low to indicate a start of
transfer. The first two bits transferred are the instruction for the slave interface of the AMIS-53000, IN1 and IN0. Following the
instruction are the six address bits to specify which address to read or write from. If the instruction is to write a register, the data to be
written to address location A<5:0> is specified with the next 8 bits, D<7:0>. If the operation is a read, the slave output buffer is enabled
at the end of the address bits, and the data bits D<7:0> are buffered out of the part MSB first.
For single read/write, the SSN line can remain active between successive read and write operations.
Figure 26: Sequential Control Register Read/Write Using the 3-Wire Interface
Figure 26 is a diagram for sequential reads or sequential writes for 3-wire control data transfer. The format of the instruction and
address is identical to that for a single read/write operation, with the address corresponding to the first register location to read or write.
The first 8 bits of data transferred correspond to the address selected. The address is internally incremented after each data byte
transferred. This task is most useful for writing to or reading from variables spanning over multiple address locations such as the
fractional PLL word (registers 03-05).
The SSN line must be de-asserted at the completion of a sequential read/write in order for the slave SPI controller to correctly interpret
the next 8 bits as a command and not data.
6.1.4. I²C Interface
The I²C interface for the AMIS-53000 is compatible with the Philip Semiconductor I²C standard, with the AMIS-53000 as the slave
device.
AMI Semiconductor – Aug. 05, Rev. 1.0
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