EP2S15 Datasheet, PDF (91/238 Pages) Altera Corporation – Stratix II Device Family

Figure 2–56. DQS Phase-Shift Circuitry Notes (1), (2), (3), (4)
DQSn
Pin
DQS
Pin
DQSn
Pin
DQS
Pin
CLK[15..12]p (2)
From PLL 5 (3)
DQS
Pin
DQSn
Pin
Δt
Δt
DQS
Δt
Δt
Phase-Shift
Δt
Δt
Circuitry
Stratix II Architecture
DQS
Pin
DQSn
Pin
Δt
Δt
DQS Logic
Blocks
to IOE
to IOE
to IOE
to IOE
to IOE
to IOE
to IOE
to IOE
Notes to Figure 2–56:
(1) There are up to 18 pairs of DQS and DQSn pins available on the top or the bottom of the Stratix II device. There are
up to 10 pairs on the right side and 8 pairs on the left side of the DQS phase-shift circuitry.
(2) The Δt module represents the DQS logic block.
(3) Clock pins CLK[15..12]p feed the phase-shift circuitry on the top of the device and clock pins CLK[7..4]p feed
the phase circuitry on the bottom of the device. You can also use a PLL clock output as a reference clock to the phase-
shift circuitry.
(4) You can only use PLL 5 to feed the DQS phase-shift circuitry on the top of the device and PLL 6 to feed the DQS
phase-shift circuitry on the bottom of the device.
f
These dedicated circuits combined with enhanced PLL clocking and
phase-shift ability provide a complete hardware solution for interfacing
to high-speed memory.
For more information on external memory interfaces, refer to the
External Memory Interfaces in Stratix II & Stratix II GX Devices chapter in
volume 2 of the Stratix II Device Handbook or the Stratix II GX Device
Handbook.
Programmable Drive Strength
The output buffer for each Stratix II device I/O pin has a programmable
drive strength control for certain I/O standards. The LVTTL, LVCMOS,
SSTL, and HSTL standards have several levels of drive strength that the
user can control. The default setting used in the Quartus II software is the
maximum current strength setting that is used to achieve maximum I/O
performance. For all I/O standards, the minimum setting is the lowest
drive strength that guarantees the I_OH/I_OL of the standard. Using
minimum settings provides signal slew rate control to reduce system
noise and signal overshoot.
Altera Corporation
May 2007
2–83
Stratix II Device Handbook, Volume 1