EP2S15 Datasheet, PDF (75/238 Pages) Altera Corporation – Stratix II Device Family

Stratix II Architecture
Table 2–12. Global & Regional Clock Connections from Bottom Clock Pins & Enhanced PLL
Outputs (Part 2 of 2)
Bottom Side Global &
Regional Clock Network
Connectivity
GCLKDRV3
RCLKDRV0
RCLKDRV1
RCLKDRV2
RCLKDRV3
RCLKDRV4
RCLKDRV5
RCLKDRV6
RCLKDRV7
Enhanced PLL 6 outputs
c0
c1
c2
c3
c4
c5
Enhanced PLL 12 outputs
c0
c1
c2
c3
c4
c5
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
vvv
v
v
vvv
v
v
v
vv
v
v
v
vv
v
v
v
v
v
v
v
v
v
v
v
v
vv
v
v
vv
v
v
vv
v
v
vv
v
v
v
v
v
v
v
v
v
v
Altera Corporation
May 2007
2–67
Stratix II Device Handbook, Volume 1