EP2S15 Datasheet, PDF (4/238 Pages) Altera Corporation – Stratix II Device Family

Features
■ Support for numerous single-ended and differential I/O standards
■ High-speed differential I/O support with DPA circuitry for 1-Gbps
performance
■ Support for high-speed networking and communications bus
standards including Parallel RapidIO, SPI-4 Phase 2 (POS-PHY
Level 4), HyperTransport™ technology, and SFI-4
■ Support for high-speed external memory, including DDR and DDR2
SDRAM, RLDRAM II, QDR II SRAM, and SDR SDRAM
■ Support for multiple intellectual property megafunctions from
Altera MegaCore^® functions and Altera Megafunction Partners
Program (AMPP^SM) megafunctions
■ Support for design security using configuration bitstream
encryption
■ Support for remote configuration updates
Table 1–1. Stratix II FPGA Family Features
Feature
ALMs
Adaptive look-up tables (ALUTs) (1)
Equivalent LEs (2)
M512 RAM blocks
M4K RAM blocks
M-RAM blocks
Total RAM bits
DSP blocks
18-bit × 18-bit multipliers (3)
Enhanced PLLs
Fast PLLs
Maximum user I/O pins
EP2S15
6,240
12,480
15,600
104
78
0
419,328
12
48
2
4
366
EP2S30 EP2S60 EP2S90 EP2S130 EP2S180
13,552 24,176 36,384 53,016 71,760
27,104 48,352 72,768 106,032 143,520
33,880 60,440 90,960 132,540 179,400
202
329
488
699
930
144
255
408
609
768
1
2
4
6
9
1,369,728 2,544,192 4,520,488 6,747,840 9,383,040
16
36
48
63
96
64
144
192
252
384
2
4
4
4
4
4
8
8
8
8
500
718
902
1,126
1,170
Notes to Table 1–1:
(1) One ALM contains two ALUTs. The ALUT is the cell used in the Quartus^® II software for logic synthesis.
(2) This is the equivalent number of LEs in a Stratix device (four-input LUT-based architecture).
(3) These multipliers are implemented using the DSP blocks.
1–2
Stratix II Device Handbook, Volume 1
Altera Corporation
May 2007