EP2S15 Datasheet, PDF (233/238 Pages) Altera Corporation – Stratix II Device Family

DC & Switching Characteristics
Table 5–102 shows the JTAG timing parameters and values for Stratix II
devices.
Table 5–102. Stratix II JTAG Timing Parameters & Values
Symbol
Parameter
Min Max Unit
t_JCP
t_JCH
t_JCL
t_JPSU
t_JPH
t_JPCO
t_JPZX
t_JPXZ
TCK clock period
TCK clock high time
TCK clock low time
JTAG port setup time
JTAG port hold time
JTAG port clock to output
JTAG port high impedance to valid output
JTAG port valid output to high impedance
30
ns
13
ns
13
ns
3
ns
5
ns
11 (1) ns
14 (1) ns
14 (1) ns
Note to Table 5–102:
(1) A 1 ns adder is required for each V_{C C I O} voltage step down from 3.3 V. For
example, t_JPCO = 12 ns if V_{C C I O} of the TDO I/O bank = 2.5 V, or 13 ns if it equals
1.8 V.
Document
Table 5–103 shows the revision history for this chapter.
Revision History
Table 5–103. Document Revision History (Part 1 of 3)
Date and
Document
Version
May 2007, v4.3
August, 2006,
v4.2
Changes Made
● Updated R_CONF in Table 5–4
● Updated f_IN (min) in Table 5–92
● Updated f_IN and f_INPFD in Table 5–93
Moved the Document Revision History section to the
end of the chapter.
● Updated Table 5–73, Table 5–75, Table 5–77,
Table 5–78, Table 5–79, Table 5–81, Table 5–85,
and Table 5–87.
Summary of Changes
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—
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Altera Corporation
May 2007
5–97
Stratix II Device Handbook, Volume 1