EP2S15 Datasheet, PDF (122/238 Pages) Altera Corporation – Stratix II Device Family

Configuration
Table 3–5. Stratix II Configuration Features (Part 2 of 2)
Configuration
Scheme
Configuration Method
PPA
JTAG
MAX II device or microprocessor and
flash device
Download cable (4)
MAX II device or microprocessor and
flash device
Design Security
Decompression
Remote System
Upgrade
v
Notes for Table 3–5:
(1) In these modes, the host system must send a DCLK that is 4× the data rate.
(2) The enhanced configuration device decompression feature is available, while the Stratix II decompression feature
is not available.
(3) Only remote update mode is supported when using the AS configuration scheme. Local update mode is not
supported.
(4) The supported download cables include the Altera USB Blaster universal serial bus (USB) port download cable,
MasterBlaster serial/USB communications cable, ByteBlaster II parallel port download cable, and the
ByteBlasterMV parallel port download cable.
f
See the Configuring Stratix II & Stratix II GX Devices chapter in volume 2
of the Stratix II Device Handbook or the Stratix II GX Device Handbook for
more information about configuration schemes in Stratix II and
Stratix II GX devices.
Device Security Using Configuration Bitstream Encryption
Stratix II FPGAs are the industry’s first FPGAs with the ability to decrypt
a configuration bitstream using the Advanced Encryption Standard
(AES) algorithm. When using the design security feature, a 128-bit
security key is stored in the Stratix II FPGA. To successfully configure a
Stratix II FPGA that has the design security feature enabled, it must be
configured with a configuration file that was encrypted using the same
128-bit security key. The security key can be stored in non-volatile
memory inside the Stratix II device. This non-volatile memory does not
require any external devices, such as a battery back-up, for storage.
3–8
Stratix II Device Handbook, Volume 1
Altera Corporation
May 2007