EP2S15 Datasheet, PDF (88/238 Pages) Altera Corporation – Stratix II Device Family

I/O Structure
Figure 2–54. Stratix II IOE in DDR Output I/O Configuration Notes (1), (2)
ioe_clk[7..0]
Column, Row,
or Local
Interconnect
oe
clkout
ce_out
OE Register
D
Q
ENA
CLRN/PRN
OE Register
tCO Delay
aclr/apreset
Chip-Wide Reset
sclr/spreset
OE Register
D
Q
ENA
CLRN/PRN
Used for
DDR, DDR2
SDRAM
VCCIO
PCI Clamp (3)
VCCIO
Programmable
Pull-Up
Resistor
Output Register
D
Q
Output
Pin Delay
ENA
CLRN/PRN
Output Register
D
Q
clk
Drive Strength
Control
Open-Drain Output
ENA
CLRN/PRN
On-Chip
Termination
Bus-Hold
Circuit
Notes to Figure 2–54:
(1) All input signals to the IOE can be inverted at the IOE.
(2) The tri-state buffer is active low. The DDIO megafunction represents the tri-state buffer as active-high with an
inverter at the OE register data port. Similarly, the aclr and apreset signals are also active-high at the input ports
of the DDIO megafunction.
(3) The optional PCI clamp is only available on column I/O pins.
2–80
Stratix II Device Handbook, Volume 1
Altera Corporation
May 2007