EP2S15 Datasheet, PDF (37/238 Pages) Altera Corporation – Stratix II Device Family

Stratix II Architecture
Table 2–3. TriMatrix Memory Features (Part 2 of 2)
Memory Feature
M512 RAM Block
(32 × 18 Bits)
M4K RAM Block
(128 × 36 Bits)
M-RAM Block
(4K × 144 Bits)
Simple dual-port memory
v
v
v
mixed width support
True dual-port memory
mixed width support
v
v
Power-up conditions
Outputs cleared
Outputs cleared
Outputs unknown
Register clears
Output registers
Output registers
Output registers
Mixed-port read-during-write Unknown output/old data Unknown output/old data Unknown output
Configurations
512 × 1
256 × 2
128 × 4
64 × 8
64 × 9
32 × 16
32 × 18
4K × 1
2K × 2
1K × 4
512 × 8
512 × 9
256 × 16
256 × 18
128 × 32
128 × 36
64K × 8
64K × 9
32K × 16
32K × 18
16K × 32
16K × 36
8K × 64
8K × 72
4K × 128
4K × 144
Notes to Table 2–3:
(1) The M-RAM block does not support memory initializations. However, the M-RAM block can emulate a ROM
function using a dual-port RAM bock. The Stratix II device must write to the dual-port memory once and then
disable the write-enable ports afterwards.
Memory Block Size
TriMatrix memory provides three different memory sizes for efficient
application support. The Quartus II software automatically partitions the
user-defined memory into the embedded memory blocks using the most
efficient size combinations. You can also manually assign the memory to
a specific block size or a mixture of block sizes.
When applied to input registers, the asynchronous clear signal for the
TriMatrix embedded memory immediately clears the input registers.
However, the output of the memory block does not show the effects until
the next clock edge. When applied to output registers, the asynchronous
clear signal clears the output registers and the effects are seen
immediately.
Altera Corporation
May 2007
2–29
Stratix II Device Handbook, Volume 1