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EP2S15 Datasheet, PDF (146/238 Pages) Altera Corporation – Stratix II Device Family
Operating Conditions
Table 5–14. 3.3-V PCI Specifications (Part 2 of 2)
Symbol
Parameter
VIL
Low-level input voltage
VOH
High-level output voltage
VOL
Low-level output voltage
Conditions
IOUT = –500 μA
IOUT = 1,500 μA
Minimum
–0.3
0.9 × VCCIO
Typical
Maximum Unit
0.3 × VCCIO V
V
0.1 × VCCIO V
Table 5–15. PCI-X Mode 1 Specifications
Symbol
Parameter
VCCIO
VIH
VIL
VIPU
VOH
VOL
Output supply voltage
High-level input voltage
Low-level input voltage
Input pull-up voltage
High-level output voltage
Low-level output voltage
Conditions
IOUT = –500 μA
IOUT = 1,500 μA
Minimum
3.0
0.5 × VCCIO
–0.30
0.7 × VCCIO
0.9 × VCCIO
Typical
Maximum Unit
3.6
V
VCCIO + 0.5 V
0.35 × VCCIO V
V
V
0.1 × VCCIO V
Table 5–16. SSTL-18 Class I Specifications
Symbol
Parameter
Conditions
Minimum Typical Maximum Unit
VCCIO
VREF
VTT
VIH (DC)
VIL (DC)
VIH (AC)
VIL (AC)
VOH
VOL
Output supply voltage
Reference voltage
Termination voltage
High-level DC input voltage
Low-level DC input voltage
High-level AC input voltage
Low-level AC input voltage
High-level output voltage
Low-level output voltage
IOH = –6.7 mA (1)
IOL = 6.7 mA (1)
1.71
0.855
VREF – 0.04
VREF + 0.125
VREF + 0.25
VTT + 0.475
1.80
0.900
VREF
1.89
V
0.945
V
VREF + 0.04 V
V
VREF – 0.125 V
V
VREF – 0.25 V
V
VTT – 0.475 V
Note to Table 5–16:
(1) This specification is supported across all the programmable drive settings available for this I/O standard as shown
in the Stratix II Architecture chapter in volume 1 of the Stratix II Device Handbook.
5–10
Stratix II Device Handbook, Volume 1
Altera Corporation
May 2007