EP2S15 Datasheet, PDF (232/238 Pages) Altera Corporation – Stratix II Device Family

JTAG Timing Specifications
Table 5–100. DQS Phase Offset Delay Per Stage Notes (1), (2), (3)
Speed Grade
-3
-4
-5
Min
Max
Unit
9
14
ps
9
14
ps
9
15
ps
Notes to Table 5–100:
(1) The delay settings are linear.
(2) The valid settings for phase offset are -64 to +63 for frequency mode 0 and -32 to
+31 for frequency modes 1, 2, and 3.
(3) The typical value equals the average of the minimum and maximum values.
Table 5–101. DDIO Outputs Half-Period Jitter Notes (1), (2)
Name
Description
Max Unit
t_{O U T H A L F J I T T E R} Half-period jitter (PLL driving DDIO outputs) 200
ps
Notes to Table 5–101:
(1) The worst-case half period is equal to the ideal half period subtracted by the DCD
and half-period jitter values.
(2) The half-period jitter was characterized using a PLL driving DDIO outputs.
JTAG Timing
Specifications
Figure 5–10 shows the timing requirements for the JTAG signals.
Figure 5–10. Stratix II JTAG Waveforms
TMS
TDI
TCK
TDO
t _JCP
t _JCH
t _JCL
t_JPZX
t _JPSU
t_JPCO
t _JPH
t _JPXZ
5–96
Stratix II Device Handbook, Volume 1
Altera Corporation
May 2007