EP2S15 Datasheet, PDF (219/238 Pages) Altera Corporation – Stratix II Device Family

DC & Switching Characteristics
Therefore, the DCD percentage for the 267 MHz SSTL-2 Class II DDIO
row output clock on a –3 device ranges from 48.4% to 51.6%.
Table 5–83. Maximum DCD for DDIO Output on Row I/O Pins Without PLL in the Clock Path for -4 & -5
Devices Notes (1), (2)
Maximum DCD Based on I/O Standard of Input Feeding the DDIO Clock
Port (No PLL in the Clock Path)
Row DDIO Output I/O
Standard
TTL/CMOS
LVDS/
SSTL-2 SSTL/HSTL HyperTransport
Unit
Technology
3.3/2.5 V 1.8/1.5 V 2.5 V 1.8/1.5 V
3.3 V
3.3-V LVTTL
440
495
170
160
105
ps
3.3-V LVCMOS
390
450
120
110
75
ps
2.5 V
375
430
105
95
90
ps
1.8 V
325
385
90
100
135
ps
1.5-V LVCMOS
430
490
160
155
100
ps
SSTL-2 Class I
355
410
85
75
85
ps
SSTL-2 Class II
350
405
80
70
90
ps
SSTL-18 Class I
335
390
65
65
105
ps
1.8-V HSTL Class I
330
385
60
70
110
ps
1.5-V HSTL Class I
330
390
60
70
105
ps
LVDS/ HyperTransport
180
180
180
180
technology
180
ps
Note to Table 5–83:
(1) Table 5–83 assumes the input clock has zero DCD.
(2) The DCD specification is based on a no logic array noise condition.
Table 5–84. Maximum DCD for DDIO Output on Column I/O Pins Without PLL in the Clock Path for -3
Devices (Part 1 of 2) Notes (1), (2)
Maximum DCD Based on I/O Standard of Input Feeding the DDIO
Clock Port (No PLL in the Clock Path)
DDIO Column Output I/O
Standard
TTL/CMOS
SSTL-2 SSTL/HSTL
1.2-V
HSTL
Unit
3.3-V LVTTL
3.3-V LVCMOS
2.5 V
3.3/2.5 V 1.8/1.5 V 2.5 V
1.8/1.5 V
1.2 V
260
380
145
145
145
ps
210
330
100
100
100
ps
195
315
85
85
85
ps
Altera Corporation
May 2007
5–83
Stratix II Device Handbook, Volume 1