EP2S15 Datasheet, PDF (200/238 Pages) Altera Corporation – Stratix II Device Family

Timing Model
Table 5–75. Stratix II I/O Output Delay for Column Pins (Part 8 of 8)
I/O Standard
Drive
Strength
Parameter
Minimum Timing
Industrial Commercial
-3
Speed
Grade
(3)
-3
Speed
Grade
(4)
-4
Speed
Grade
-5
Speed
Grade
Unit
1.5-V
16 mA t_{O P}
Differential
HSTL Class II
t_{D I P}
18 mA t_{O P}
t_{D I P}
20 mA t_{O P}
t_{D I P}
881
901
884
904
886
906
924
1431 1501 1644 1734 ps
946
1497 1571 1720 1824 ps
927
1439 1510 1654 1744
949
1505 1580 1730 1834
929
1450 1521 1666 1757
951
1516 1591 1742 1847
Notes to Table 5–75:
(1) This is the default setting in the Quartus II software.
(2) These I/O standards are only supported on DQS pins.
(3) These numbers apply to -3 speed grade EP2S15, EP2S30, EP2S60, and EP2S90 devices.
(4) These numbers apply to -3 speed grade EP2S130 and EP2S180 devices.
Table 5–76. Stratix II I/O Output Delay for Row Pins (Part 1 of 3)
I/O Standard
LVTTL
LVCMOS
Drive
Strength
Parameter
4 mA
t_{O P}
t_{D I P}
8 mA
t_{O P}
t_{D I P}
12 mA t_{O P}
(1)
t_{D I P}
4 mA
t_{O P}
t_{D I P}
8 mA (1) t_{O P}
t_{D I P}
Minimum Timing
Industrial Commercial
-3
Speed
Grade
(2)
-3
Speed
Grade
(3)
-4
Speed
Grade
-5
Speed
Grade
Unit
1267
1328
2655 2786 3052 3189 ps
1225
1285
2600 2729 2989 3116 ps
1144
1200
2113 2217 2429 2549 ps
1102
1157
2058 2160 2366 2476 ps
1091
1144
2081 2184 2392 2512 ps
1049
1101
2026 2127 2329 2439 ps
1144
1200
2113 2217 2429 2549 ps
1102
1157
2058 2160 2366 2476 ps
1044
1094
1853 1944 2130 2243 ps
1002
1051
1798 1887 2067 2170 ps
5–64
Stratix II Device Handbook, Volume 1
Altera Corporation
May 2007