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EP2S15 Datasheet, PDF (112/238 Pages) Altera Corporation – Stratix II Device Family | |||
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Document Revision History
Document
Table 2â27 shows the revision history for this chapter.
Revision History
Table 2â27. Document Revision History (Part 1 of 2)
Date and
Document
Version
Changes Made
Summary of Changes
May 2007, v4.3 Updated âClock Control Blockâ section.
â
Updated note in the âClock Control Blockâ section.
â
Deleted Tables 2-11 and 2-12.
â
Updated notes to:
â
â Figure 2â41
â Figure 2â42
â Figure 2â43
â Figure 2â45
Updated notes to Table 2â18.
â
Moved Document Revision History to end of the chapter.
â
August 2006, Updated Table 2â18 with note.
â
v4.2
April 2006,
v4.1
â Updated Table 2â13.
â Removed Note 2 from Table 2â16.
â Updated âOn-Chip Terminationâ section and Table 2â19 to
include parallel termination with calibration information.
â Added new âOn-Chip Parallel Termination with Calibrationâ
section.
â Updated Figure 2â44.
â Added parallel on-
chip termination
description and
specification.
â Changed RCLK
names to match the
Quartus II software in
Table 2â13.
December
Updated âClock Control Blockâ section.
â
2005, v4.0
July 2005, v3.1 â Updated HyperTransport technology information in Table 2â18.
â
â Updated HyperTransport technology information in
Figure 2â57.
â Added information on the asynchronous clear signal.
May 2005, v3.0 â Updated âFunctional Descriptionâ section.
â
â Updated Table 2â3.
â Updated âClock Control Blockâ section.
â Updated Tables 2â17 through 2â19.
â Updated Tables 2â20 through 2â22.
â Updated Figure 2â57.
March 2005, â Updated âFunctional Descriptionâ section.
â
2.1
â Updated Table 2â3.
2â104
Stratix II Device Handbook, Volume 1
Altera Corporation
May 2007
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