EP2S15 Datasheet, PDF (39/238 Pages) Altera Corporation – Stratix II Device Family

Stratix II Architecture
Figure 2–19. M512 RAM Block Control Signals
Dedicated
6
Row LAB
Clocks
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
inclocken
outclocken
wren
inclock
outclock
rden
outclr
Altera Corporation
May 2007
2–31
Stratix II Device Handbook, Volume 1