EP2S15 Datasheet, PDF (24/238 Pages) Altera Corporation – Stratix II Device Family

Adaptive Logic Modules
Figure 2–12. Conditional Operation Example
ALM 1
Adder output
is not used.
X[0]
Y[0]
syncdata
X[1]
Y[1]
Carry Chain
Comb & _X[0]
Adder
Logic
Comb &
Adder
Logic
syncload
X[1]
syncload
R[0]
DQ
reg0
R[1]
DQ
reg1
ALM 2
To general or
local routing
To general or
local routing
X[2]
Comb &
Adder ^X[2]
Y[2]
Logic
R[2]
DQ
To general or
local routing
syncload
reg0
Comb &
Adder
Logic
carry_out
To local routing &
then to LAB-wide
syncload
The arithmetic mode also offers clock enable, counter enable,
synchronous up/down control, add/subtract control, synchronous clear,
synchronous load. The LAB local interconnect data inputs generate the
clock enable, counter enable, synchronous up/down and add/subtract
control signals. These control signals are good candidates for the inputs
that are shared between the four LUTs in the ALM. The synchronous clear
and synchronous load options are LAB-wide signals that affect all
registers in the LAB. The Quartus II software automatically places any
registers that are not used by the counter into other LABs.
Carry Chain
The carry chain provides a fast carry function between the dedicated
adders in arithmetic or shared arithmetic mode. Carry chains can begin in
either the first ALM or the fifth ALM in an LAB. The final carry-out signal
is routed to an ALM, where it is fed to local, row, or column interconnects.
2–16
Stratix II Device Handbook, Volume 1
Altera Corporation
May 2007