EP2S15 Datasheet, PDF (162/238 Pages) Altera Corporation – Stratix II Device Family

Timing Model
Figure 5–6. Measurement Setup for t_zx
t_ZX, Tristate to Driving High
Disable Enable
OE
OE
½ V_CCINT
Dout
Din
Din
1 MΩ
Dout
t_zh
t_ZX, Tristate to Driving Low
Disable Enable
OE
½ V_CCINT
1 MΩ
OE
Dout _Din
Din
Dout
t_zl
“1”
½ V_CCIO
“0”
½ V_CCIO
Table 5–35 specifies the input timing measurement setup.
Table 5–35. Timing Measurement Methodology for Input Pins (Part 1 of 2) Notes (1)–(4)
I/O Standard
LVTTL (5)
LVCMOS (5)
2.5 V (5)
1.8 V (5)
1.5 V (5)
PCI (6)
PCI-X (6)
SSTL-2 Class I
SSTL-2 Class II
SSTL-18 Class I
SSTL-18 Class II
1.8-V HSTL Class I
Measurement Conditions
Measurement Point
V_CCIO (V)
3.135
3.135
2.375
1.710
1.425
2.970
2.970
2.325
2.325
1.660
1.660
1.660
V_REF (V)
1.163
1.163
0.830
0.830
0.830
Edge Rate (ns)
3.135
3.135
2.375
1.710
1.425
2.970
2.970
2.325
2.325
1.660
1.660
1.660
V_{M E A S} (V)
1.5675
1.5675
1.1875
0.855
0.7125
1.485
1.485
1.1625
1.1625
0.83
0.83
0.83
5–26
Stratix II Device Handbook, Volume 1
Altera Corporation
May 2007