EP2S15 Datasheet, PDF (135/238 Pages) Altera Corporation – Stratix II Device Family

Hot Socketing & Power-On Reset
Figure 4–2. Transistor Level Diagram of FPGA Device I/O Buffers
Logic Array
V_PAD
Signal
(1)
(2)
V_CCIO
n+
n+
p-well
p+
p+
n+
n-well
p-substrate
Notes to Figure 4–2:
(1) This is the logic array signal or the larger of either the V_CCIO or V_PAD signal.
(2) This is the larger of either the V_CCIO or V_PAD signal.
Power-On Reset
Circuitry
Stratix II devices have a POR circuit to keep the whole device system in
reset state until the power supply voltage levels have stabilized during
power-up. The POR circuit monitors the V_CCINT, V_CCIO, and V_CCPD voltage
levels and tri-states all the user I/O pins while V_CC is ramping up until
normal user levels are reached. The POR circuitry also ensures that all
eight I/O bank V_CCIO voltages, V_CCPD voltage, as well as the logic array
V_CCINT voltage, reach an acceptable level before configuration is
triggered. After the Stratix II device enters user mode, the POR circuit
continues to monitor the V_CCINT voltage level so that a brown-out
condition during user mode can be detected. If there is a V_CCINT voltage
sag below the Stratix II operational level during user mode, the POR
circuit resets the device.
When power is applied to a Stratix II device, a power-on-reset event
occurs if V_CC reaches the recommended operating range within a certain
period of time (specified as a maximum V_CC rise time). The maximum
V_CC rise time for Stratix II device is 100 ms. Stratix II devices provide a
dedicated input pin (PORSEL) to select POR delay times of 12 or 100 ms
during power-up. When the PORSEL pin is connected to ground, the POR
time is 100 ms. When the PORSEL pin is connected to V_CC, the POR time
is 12 ms.
Altera Corporation
May 2007
4–5
Stratix II Device Handbook, Volume 1