EP2S15 Datasheet, PDF (177/238 Pages) Altera Corporation – Stratix II Device Family

DC & Switching Characteristics
Table 5–42. M-RAM Block Internal Timing Microparameters (Part 2 of 2) Note (1)
Symbol
t_{M E G A C L K H}
t_{M E G A C L R}
Parameter
Minimum clock high
time
Minimum clear pulse
width
-3 Speed
Grade (2)
Min
(4)
Max
-3 Speed
Grade (3)
Min
(4)
Max
-4 Speed
Grade
Min
(5)
Max
-5 Speed
Grade
Unit
Min
(4)
Max
1,250
1,312
1,437
1,675
ps
1,437
144
151
165
192
ps
165
Notes to Table 5–42:
(1) F_MAX of M-RAM Block obtained using the Quartus II software does not necessarily equal to 1/TMEGARC.
(2) These numbers apply to -3 speed grade EP2S15, EP2S30, EP2S60, and EP2S90 devices.
(3) These numbers apply to -3 speed grade EP2S130 and EP2S180 devices.
(4) For the -3 and -5 speed grades, the minimum timing is for the commercial temperature grade. Only -4 speed grade
devices offer the industrial temperature grade.
(5) For the -4 speed grade, the first number is the minimum timing parameter for industrial devices. The second
number is the minimum timing parameter for commercial devices.
Stratix II Clock Timing Parameters
See Tables 5–43 through 5–67 for Stratix II clock timing parameters.
Table 5–43. Stratix II Clock Timing Parameters
Symbol
t_{C I N}
t_{C O U T}
t_{P L L C I N}
t_{P L L C O U T}
Parameter
Delay from clock pad to I/O input register
Delay from clock pad to I/O output register
Delay from PLL inclk pad to I/O input register
Delay from PLL inclk pad to I/O output register
Altera Corporation
May 2007
5–41
Stratix II Device Handbook, Volume 1