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EP2S15 Datasheet, PDF (221/238 Pages) Altera Corporation – Stratix II Device Family | |||
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DC & Switching Characteristics
Table 5â85. Maximum DCD for DDIO Output on Column I/O Pins Without PLL in the Clock Path for -4 & -5
Devices (Part 2 of 2) Notes (1), (2)
DDIO Column Output I/O
Standard
Maximum DCD Based on I/O Standard of Input Feeding the DDIO
Clock Port (No PLL in the Clock Path)
TTL/CMOS
SSTL-2
SSTL/HSTL
Unit
SSTL-18 Class I
SSTL-18 Class II
1.8-V HSTL Class I
1.8-V HSTL Class II
1.5-V HSTL Class I
1.5-V HSTL Class II
1.2-V HSTL
LVPECL
3.3/2.5 V
335
320
330
330
330
330
420
180
1.8/1.5 V
390
375
385
385
390
360
470
180
2.5 V
65
70
60
60
60
90
155
180
1.8/1.5 V
65
ps
80
ps
70
ps
70
ps
70
ps
100
ps
165
ps
180
ps
Note to Table 5â85:
(1) Table 5â85 assumes the input clock has zero DCD.
(2) The DCD specification is based on a no logic array noise condition.
Table 5â86. Maximum DCD for DDIO Output on Row I/O Pins with PLL in the
Clock Path (Part 1 of 2) Note (1)
Row DDIO Output I/O
Standard
3.3-V LVTTL
3.3-V LVCMOS
2.5V
1.8V
1.5-V LVCMOS
SSTL-2 Class I
SSTL-2 Class II
SSTL-18 Class I
1.8-V HSTL Class I
1.5-V HSTL Class I
Maximum DCD (PLL Output Clock Feeding
DDIO Clock Port)
Unit
-3 Device
-4 & -5 Device
110
105
ps
65
75
ps
75
90
ps
85
100
ps
105
100
ps
65
75
ps
60
70
ps
50
65
ps
50
70
ps
55
70
ps
Altera Corporation
May 2007
5â85
Stratix II Device Handbook, Volume 1
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