EP2S15 Datasheet, PDF (68/238 Pages) Altera Corporation – Stratix II Device Family

PLLs & Clock Networks
Figure 2–40 shows a top-level diagram of the Stratix II device and PLL
floorplan.
Figure 2–40. PLL Locations
FPLL7CLK 7
CLK[15..12]
11 5
10 FPLL10CLK
1
CLK[3..0]
2
4
CLK[8..11]
3
PLLs
FPLL8CLK 8
12 6
CLK[7..4]
9 FPLL9CLK
Figures 2–41 and 2–42 shows the global and regional clocking from the
fast PLL outputs and the side clock pins.
2–60
Stratix II Device Handbook, Volume 1
Altera Corporation
May 2007