EP2S15 Datasheet, PDF (209/238 Pages) Altera Corporation – Stratix II Device Family

DC & Switching Characteristics
Table 5–78. Maximum Output Toggle Rate on Stratix II Devices (Part 5 of 5) Note (1)
I/O Standard
1.2-V Differential
HSTL
Drive
Strength
OCT 50 Ω
Column I/O Pins (MHz)
-3
-4
-5
280
-
-
Row I/O Pins (MHz)
-3
-4 -5
-
-
-
Clock Outputs (MHz)
-3 -4 -5
280 -
-
Notes to Table 5–78:
(1) The toggle rate applies to 0-pF output load for all I/O standards except for LVDS and HyperTransport technology
on row I/O pins. For LVDS and HyperTransport technology on row I/O pins, the toggle rates apply to load from
0 to 5pF.
(2) 1.2-V HSTL is only supported on column I/O pins in I/O banks 4, 7, and 8.
(3) Differential HSTL and SSTL is only supported on column clock and DQS outputs.
(4) HyperTransport technology is only supported on row I/O and row dedicated clock input pins.
(5) LVPECL is only supported on column clock pins.
(6) Refer to Tables 5–81 through 5–91 if using SERDES block. Use the toggle rate values from the clock output column
for PLL output.
Table 5–79. Maximum Output Clock Toggle Rate Derating Factors (Part 1 of 5)
I/O Standard
Drive
Strength
3.3-V LVTTL
3.3-V LVCMOS
2.5-V
LVTTL/LVCMOS
4 mA
8 mA
12 mA
16 mA
20 mA
24 mA
4 mA
8 mA
12 mA
16 mA
20 mA
24 mA
4 mA
8 mA
12 mA
16 mA
Maximum Output Clock Toggle Rate Derating Factors (ps/pF)
Column I/O Pins
Row I/O Pins
Dedicated Clock Outputs
-3
-4
-5
-3
-4
-5
-3 -4
-5
478 510 510 478 510 510 466 510 510
260 333 333 260 333 333 291 333 333
213 247 247 213 247 247 211 247 247
136 197 197
-
-
-
166 197 197
138 187 187
-
-
-
154 187 187
134 177 177
-
-
-
143 177 177
377 391 391 377 391 391 377 391 391
206 212 212 206 212 212 178 212 212
141 145 145
-
-
-
115 145 145
108 111 111
-
-
-
86 111 111
83
88
88
-
-
-
79 88
88
65
72
72
-
-
-
74 72
72
387 427 427 387 427 427 391 427 427
163 224 224 163 224 224 170 224 224
142 203 203 142 203 203 152 203 203
120 182 182
-
-
-
134 182 182
Altera Corporation
May 2007
5–73
Stratix II Device Handbook, Volume 1