EP20K200C Datasheet, PDF (86/90 Pages) Altera Corporation – Programmable Logic

APEX 20KC Programmable Logic Device Data Sheet
Table 69. Selectable I/O Standard Output Delays
Symbol
-7 Speed Grade
-8 Speed Grad
-9 Speed Grade
Unit
LVCMOS
LVTTL
2.5 V
1.8 V
PCI
GTL+
SSTL-3 Class I
SSTL-3 Class II
SSTL-2 Class I
SSTL-2 Class II
LVDS
CTT
AGP
Min
Max
Min
Max
Min
Max
Min
0.00
0.00
0.00
1.18
–0.52
–0.18
–0.67
–0.67
–0.67
–0.67
–0.69
0.00
0.00
0.00
0.00
0.00
1.41
–0.53
–0.29
–0.71
–0.71
–0.71
–0.71
–0.70
0.00
0.00
0.00
ns
0.00
ns
0.00
ns
1.57
ns
–0.56
ns
–0.39
ns
–0.75
ns
–0.75
ns
–0.75
ns
–0.75
ns
–0.73
ns
0.00
ns
0.00
ns
Power
Consumption
To estimate device power consumption, use the interactive power
estimator on the Altera web site at http://www.altera.com.
Configuration &
Operation
The APEX 20KC architecture supports several configuration schemes.
This section summarizes the device operating modes and available device
configuration schemes.
Operating Modes
The APEX architecture uses SRAM configuration elements that require
configuration data to be loaded each time the circuit powers up. The
process of physically loading the SRAM data into the device is called
configuration. During initialization, which occurs immediately after
configuration, the device resets registers, enables I/O pins, and begins to
operate as a logic device. The I/O pins are tri-stated during power-up,
and before and during configuration. Together, the configuration and
initialization processes are called command mode; normal device operation
is called user mode.
Before and during device configuration, all I/O pins are pulled to V_CCIO
by a built-in weak pull-up resistor.
86
Altera Corporation