EP20K200C Datasheet, PDF (5/90 Pages) Altera Corporation – Programmable Logic

APEX 20KC Programmable Logic Device Data Sheet
APEX 20KC devices include additional features such as enhanced I/O
standard support, CAM, additional global clocks, and enhanced
ClockLock clock circuitry. Table 7 shows the features included in
APEX 20KC devices.
Table 7. APEX 20KC Device Features (Part 1 of 2)
Feature
MultiCore system integration
Hot-socketing support
SignalTap logic analysis
32-/64-bit, 33-MHz PCI
32-/64-bit, 66-MHz PCI
MultiVolt I/O
ClockLock support
Dedicated clock and input pins
APEX 20KC Devices
Full support
Full support
Full support
Full compliance
Full compliance in -7 and -8 speed grades in
selected devices
1.8-V, 2.5-V, or 3.3-V V_CCIO
V_CCIO selected bank by bank
5.0-V tolerant with use of external resistor
Clock delay reduction
m /(n × v) clock multiplication
Drive ClockLock output off-chip
External clock feedback
ClockShift circuitry
LVDS support
Up to four PLLs
ClockShift clock phase adjustment
Eight
Altera Corporation
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