EP20K200C Datasheet, PDF (68/90 Pages) Altera Corporation – Programmable Logic

APEX 20KC Programmable Logic Device Data Sheet
Figure 35. Synchronous Bidirectional Pin External Timing
Dedicated
Clock
OE Register (1)
PRN
DQ
CLRN
Output IOE Register
PRN
DQ
t_XZBIDIR
t_ZXBIDIR
t_OUTCOBIDIR
Bidirectional Pin
CLRN
Input Register (1), (2)
PRN
DQ
t_INSUBIDIR
t_INHBIDIR
CLRN
Notes to Figure 35:
(1) The output enable and input registers are LE registers in the LAB adjacent to the
bidirectional pin. Use the “Output Enable Routing = Single-Pin” option in the
Quartus II software to set the output enable register.
(2) Use the “Decrease Input Delay to Internal Cells = OFF” option in the Quartus II
software to set the LAB-adjacent input register. This maintains a zero hold time for
LAB-adjacent registers while giving a fast, position-independent setup time. Set
“Decrease Input Delay to Internal Cells = ON” and move the input register farther
away from the bidirectional pin for a faster setup time with zero hold time. The
exact position where zero hold occurs with the minimum setup time varies with
device density and speed grade.
Tables 36 to 38 describes the f_MAX timing parameters shown in Figure 32.
Table 39 describes the functional timing parameters.
Table 36. APEX 20KC f_MAX LE Timing Parameters
Symbol
Parameter
t_SU
LE register setup time before clock
t_H
LE register hold time before clock
t_CO
LE register clock-to-output delay
t_LUT
LUT delay for data-in to data-out
68
Altera Corporation