EP20K200C Datasheet, PDF (71/90 Pages) Altera Corporation – Programmable Logic

APEX 20KC Programmable Logic Device Data Sheet
Table 41. APEX 20KC External Bidirectional Timing Parameters Note (1)
Symbol
Parameter
Condition
t_INSUBIDIR
t_INHBIDIR
t_OUTCOBIDIR
t_XZBIDIR
t_ZXBIDIR
t_INSUBIDIRPLL
t_INHBIDIRPLL
t_{OUTCOBIDIRPLL}
t_XZBIDIRPLL
t_ZXBIDIRPLL
Setup time for bidirectional pins with global clock at LAB-adjacent input
register
Hold time for bidirectional pins with global clock at LAB-adjacent input
register
Clock-to-output delay for bidirectional pins with global clock at IOE
(2)
register
Synchronous output enable register to output buffer disable delay
(2)
Synchronous output enable register to output buffer enable delay
(2)
Setup time for bidirectional pins with PLL clock at LAB-adjacent input
register
Hold time for bidirectional pins with PLL clock at LAB-adjacent input
register
Clock-to-output delay for bidirectional pins with PLL clock at IOE register (2)
Synchronous output enable register to output buffer disable delay with (2)
PLL
Synchronous output enable register to output buffer enable delay with (2)
PLL
Notes to Tables 40 and 41:
(1) These timing parameters are sample-tested only.
(2) For more information, refer to Table 43.
Tables 42 and 43 define the timing delays for each I/O standard. Some
output standards require test load circuits for AC timing measurements as
shown in Figures 36 through 38.
Table 42. APEX 20KC Selectable I/O Standard Input Adder Delays (Part 1 of 2) Note (1)
Symbol
LVCMOS
LVTTL
2.5 V
1.8 V
PCI
GTl+
SSTL-3 Class I
SSTL-3 Class II
SSTL-2 Class I
SSTL-2 Class II
Parameter
Input adder delay for the LVCMOS I/O standard
Input adder delay for the LVTTL I/O standard
Input adder delay for the 2.5-V I/O standard
Input adder delay for the 1.8-V I/O standard
Input adder delay for the PCI I/O standard
Input adder delay for the GTL+ I/O standard
Input adder delay for the SSTL-3 Class I I/O standard
Input adder delay for the SSTL-3 Class II I/O standard
Input adder delay for the SSTL -2 Class I I/O standard
Input adder delay for the SSTL -2 Class II I/O standard
Condition
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