EP20K200C Datasheet, PDF (46/90 Pages) Altera Corporation – Programmable Logic

APEX 20KC Programmable Logic Device Data Sheet
ClockLock &
ClockBoost
Features
Open-drain output pins on APEX 20KC devices (with a series resistor and
a pull-up resistor to the 5.0-V supply) can drive 5.0-V CMOS input pins
that require a V_IH of 3.5 V. When the pin is inactive, the trace will be pulled
up to 5.0 V by the resistor. The open-drain pin will only drive low or tri-
state; it will never drive high. The rise time is dependent on the value of
the pull-up resistor and load impedance. The I_OL current specification
should be considered when selecting a pull-up resistor.
APEX 20KC devices support the ClockLock and ClockBoost clock
management features, which are implemented with PLLs. The ClockLock
circuitry uses a synchronizing PLL that reduces the clock delay and skew
within a device. This reduction minimizes clock-to-output and setup
times while maintaining zero hold times. The ClockBoost circuitry, which
provides a clock multiplier, allows the designer to enhance device area
efficiency by sharing resources within the device. The ClockBoost
circuitry allows the designer to distribute a low-speed clock and multiply
that clock on-device. APEX 20KC devices include a high-speed clock tree;
unlike ASICs, the user does not have to design and optimize the clock tree.
The ClockLock and ClockBoost features work in conjunction with the
APEX 20KC device’s high-speed clock to provide significant
improvements in system performance and bandwidth. APEX 20KC
devices in -7 and -8 speed grades have PLLs and support the ClockLock
and ClockBoost features.
The ClockLock and ClockBoost features in APEX 20KC devices are
enabled through the Quartus II software. External devices are not
required to use these features.
APEX 20KC ClockLock Feature
APEX 20KC devices include up to four PLLs, which can be used
independently. Two PLLs are designed for either general-purpose use or
LVDS use (on devices that support LVDS I/O pins). The remaining two
PLLs are designed for general-purpose use. The EP20K200C devices have
two PLLs; the EP20K400C and larger devices have four PLLs.
The following sections describe some of the features offered by the
APEX 20KC PLLs.
External PLL Feedback
The ClockLock circuit’s output can be driven off-chip to clock other
devices in the system; further, the feedback loop of the PLL can be routed
off-chip. This feature allows the designer to exercise fine control over the
I/O interface between the APEX 20KC device and another high-speed
device, such as SDRAM.
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Altera Corporation