EP20K200C Datasheet, PDF (50/90 Pages) Altera Corporation – Programmable Logic

APEX 20KC Programmable Logic Device Data Sheet
Table 12. APEX 20KC Clock Input & Output Parameters (Part 2 of 2) Note (1)
Symbol
Parameter
I/O Standard -7 Speed Grade -8 Speed Grade Units
Min Max Min Max
f_{CLOCK1_EXT} Output clock frequency for
3.3-V LVTTL
(5)
(5)
(5)
(5) MHz
external clock1 output
2.5-V LVTTL
(5)
(5)
(5)
(5) MHz
1.8-V LVTTL
(5)
(5)
(5)
(5) MHz
GTL+
(5)
(5)
(5)
(5) MHz
SSTL-2 Class I (5)
(5)
(5)
(5) MHz
SSTL-2 Class II (5)
(5)
(5)
(5) MHz
SSTL-3 Class I (5)
(5)
(5)
(5) MHz
SSTL-3 Class II (5)
(5)
(5)
(5) MHz
LVDS
(5)
(5)
(5)
(5) MHz
f_IN
Input clock frequency
3.3-V LVTTL
(5)
(5)
(5)
(5) MHz
2.5-V LVTTL
(5)
(5)
(5)
(5) MHz
1.8-V LVTTL
(5)
(5)
(5)
(5) MHz
GTL+
(5)
(5)
(5)
(5) MHz
SSTL-2 Class I (5)
(5)
(5)
(5) MHz
SSTL-2 Class II (5)
(5)
(5)
(5) MHz
SSTL-3 Class I (5)
(5)
(5)
(5) MHz
SSTL-3 Class II (5)
(5)
(5)
(5) MHz
LVDS
(5)
(5)
(5)
(5) MHz
Notes to Tables 11 and 12:
(1) All input clock specifications must be met. The PLL may not lock onto an incoming clock if the clock specifications
are not met, creating an erroneous clock within the device.
(2) The maximum lock time is 40 µs or 2,000 input clock cycles, whichever occurs first.
(3) Before configuration, the PLL circuits are disable and powered down. During configuration, the PLLs remain
disabled. The PLLs begin to lock once the device is in the user mode. If the clock enable feature is used, lock begins
once the CLKLK_ENA pin goes high in user mode.
(4) The PLL VCO operating range is 200 MHz ≤ f_VCO ≤ 840 MHz for LVDS mode.
(5) Contact Altera Applications for information on these parameters.
SignalTap
Embedded
Logic Analyzer
APEX 20KC devices include device enhancements to support the
SignalTap embedded logic analyzer. By including this circuitry, the
APEX 20KC device provides the ability to monitor design operation over
a period of time through the IEEE Std. 1149.1 (JTAG) circuitry; a designer
can analyze internal logic at speed without bringing internal signals to the
I/O pins. This feature is particularly important for advanced packages
such as FineLine BGA packages because adding a connection to a pin
during the debugging process can be difficult after a board is designed
and manufactured.
50
Altera Corporation