EP20K200C Datasheet, PDF (44/90 Pages) Altera Corporation – Programmable Logic

APEX 20KC Programmable Logic Device Data Sheet
Figure 28. APEX 20KC I/O Banks
I/O Bank 1
I/O Bank 2
I/O Bank 8
LVDS Output
Block (2)
(1)
I/O Bank 7
Regular I/O Banks Support
■ LVPECL
■ LVTTL
■ LVCMOS
■ 2.5 V
■ 1.8 V
■ 3.3-V PCI
■ GTL+
■ HSTL
■ SSTL-2 Class I and II
■ SSTL-3 Class I and II
■ CTT
■ AGP
Individual
Power Bus
I/O Bank 3
(1)
LVDS Input
Block (2)
I/O Bank 4
I/O Bank 6
I/O Bank 5
Notes to Figure 28:
(1) For more information on placing I/O pins in LVDS blocks, refer to the “Guidelines for Using LVDS Blocks” section
in Application Note 120 (Using LVDS in APEX 20KE Devices).
(2) If the LVDS input and output blocks are not used for LVDS, they can support all of the I/O standards and can be
used as input, output, or bidirectional pins with V_CCIO set to 3.3 V, 2.5 V, or 1.8 V.
Power Sequencing & Hot Socketing
Because APEX 20KC devices can be used in a mixed-voltage environment,
they have been designed specifically to tolerate any possible power-up
sequence. Therefore, the V_CCIO and V_CCINT power supplies may be
powered in any order.
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Altera Corporation