EP20K200C Datasheet, PDF (26/90 Pages) Altera Corporation – Programmable Logic

APEX 20KC Programmable Logic Device Data Sheet
Figure 14. APEX 20KC Macrocell
ESB-Wide ESB-Wide ESB-Wide
Clears Clock Enables Clocks
2
2
2
Parallel Logic
Expanders
(From Other
Macrocells)
Programmable
Register
Product-
Term
Select
Matrix
Clock/
Enable
Select
DQ
ENA
CLRN
ESB
Output
32 Signals
from Local
Interconnect
Clear
Select
For registered functions, each macrocell register can be programmed
individually to implement D, T, JK, or SR operation with programmable
clock control. The register can be bypassed for combinatorial operation.
During design entry, the designer specifies the desired register type; the
Quartus II software then selects the most efficient register operation for
each registered function to optimize resource utilization. The Quartus II
software or other synthesis tools can also select the most efficient register
operation automatically when synthesizing HDL designs.
Each programmable register can be clocked by one of two ESB-wide
clocks. The ESB-wide clocks can be generated from device dedicated clock
pins, global signals, or local interconnect. Each clock also has an
associated clock enable, generated from the local interconnect. The clock
and clock enable signals are related for a particular ESB; any macrocell
using a clock also uses the associated clock enable.
If both the rising and falling edges of a clock are used in an ESB, both
ESB-wide clock signals are used.
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Altera Corporation