EP20K200C Datasheet, PDF (38/90 Pages) Altera Corporation – Programmable Logic

APEX 20KC Programmable Logic Device Data Sheet
APEX 20KC devices include an enhanced IOE, which drives the FastRow
interconnect. The FastRow interconnect connects a column I/O pin
directly to the LAB local interconnect within two MegaLAB structures.
This feature provides fast setup times for pins that drive high fan-outs
with complex logic, such as PCI designs. For fast bidirectional I/O timing,
LE registers using local routing can improve setup times and OE timing.
The APEX 20KC IOE also includes direct support for open-drain
operation, giving faster clock-to-output for open-drain signals. Some
programmable delays in the APEX 20KC IOE offer multiple levels of
delay to fine-tune setup and hold time requirements. The Quartus II
Compiler sets these delays by default to minimize setup time while
providing a zero hold time.
The Quartus II Compiler uses the programmable inversion option to
invert signals from the row and column interconnect automatically where
appropriate. Because the APEX 20KC IOE offers one output enable per
pin, the Quartus II Compiler can emulate open-drain operation efficiently.
The APEX 20KC IOE includes programmable delays that can be activated
to ensure zero hold times, minimum clock-to-output times, input IOE
register-to-core register transfers, or core-to-output IOE register transfers.
A path in which a pin directly drives a register may require the delay to
ensure zero hold time, whereas a path in which a pin drives a register
through combinatorial logic may not require the delay.
Table 9 describes the APEX 20KC programmable delays and their logic
options in the Quartus II software.
Table 9. APEX 20KC Programmable Delay Chains
Programmable Delay
Input pin to core delay
Input pin to input register delay
Core to output register delay
Output register t_CO delay
Clock enable delay
Quartus II Logic Option
Decrease input delay to internal cells
Decrease input delay to input registers
Decrease input delay to output register
Increase delay to output pin
Increase clock enable delay
The Quartus II Compiler can program these delays automatically to
minimize setup time while providing a zero hold time.
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