EP20K200C Datasheet, PDF (17/90 Pages) Altera Corporation – Programmable Logic

APEX 20KC Programmable Logic Device Data Sheet
Figure 8. APEX 20KC LE Operating Modes
Normal Mode (1)
Carry-In (3)
Cascade-In
LAB-Wide
Clock Enable (2)
data1
data2
data3
data4
4-Input
LUT
PRN
DQ
ENA
CLRN
Cascade-Out
LE Out
LE Out
Arithmetic Mode
Carry-In
data1
data2
Cascade-In
LAB-Wide
Clock Enable (2)
3-Input
LUT
3-Input
LUT
Carry-Out Cascade-Out
PRN
DQ
ENA
CLRN
LE Out
LE Out
Counter Mode
(4)
data1 (5)
data2 (5)
data3 (data)
Carry-In
Cascade-In
LAB-Wide
Synchronous
Clear (6)
LAB-Wide
Synchronous LAB-Wide
Load (6)
Clock Enable (2)
3-Input
LUT
3-Input
LUT
Carry-Out Cascade-Out
PRN
DQ
ENA
CLRN
LE Out
LE Out
Notes to Figure 8:
(1) LEs in normal mode support register packing.
(2) There are two LAB-wide clock enables per LAB.
(3) When using the carry-in in normal mode, the packed register feature is unavailable.
(4) A register feedback multiplexer is available on LE1 of each LAB.
(5) The DATA1 and DATA2 input signals can supply counter enable, up or down control, or register feedback signals for
LEs other than the second LE in an LAB.
(6) The LAB-wide synchronous clear and LAB wide synchronous load affect all registers in an LAB.
Altera Corporation
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