EP20K200C Datasheet, PDF (65/90 Pages) Altera Corporation – Programmable Logic

Timing Model
APEX 20KC Programmable Logic Device Data Sheet
The high-performance FastTrack and MegaLAB interconnect routing
resources ensure predictable performance, accurate simulation, and
accurate timing analysis. This predictable performance contrasts with that
of FPGAs, which use a segmented connection scheme and therefore have
unpredictable performance.
Figure 32 shows the f_MAX timing model for APEX 20KC devices.
Figure 32. f_MAX Timing Model
LE
t _SU
tH
t _CO
t _LUT
Routing Delay
t _F1—4
t _F5—20
t
F20+
ESB
t _ESBARC
t _ESBSRC
t _ESBAWC
t _ESBSWC
t _ESBWASU
t _ESBWDSU
t _ESBSRASU
t _ESBWESU
t _ESBDATASU
t _ESBWADDRSU
t _ESBRADDRSU
t _ESBDATACO1
t _ESBDATACO2
t _ESBDD
t _PD
t _PTERMSU
t _PTERMCO
Figures 33 and 34 show the asynchronous and synchronous
timingwaveforms, respectively, for the ESB macroparameters in Table 37.
Altera Corporation
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