EP20K200C Datasheet, PDF (40/90 Pages) Altera Corporation – Programmable Logic

APEX 20KC Programmable Logic Device Data Sheet
Figure 25. APEX 20KC Bidirectional I/O Registers
Row, Column, FastRow, 4 Dedicated
or Local Interconnect Clock Inputs
4 Dedicated Peripheral Control
Inputs
Bus
Notes (1), (2)
OE Register
DQ
VCC
ENA
CLRN
OE[7..0]
Chip-Wide Reset
VCC
Chip-Wide
Output Enable
12
4 _VCC
CLK[1..0]
CLK[3..0]
ENA[5..0]
CLRn[1..0]
Input Pin to
Core Delay (1)
Input Pin to
Core Delay (1)
Core to Output
Register Delay
Input Pin to Input
Register Delay
Output Register
DQ
ENA
CLRN/
PRN
VCC
Clock Enable
Delay (1)
VCC
Output Register
tCO Delay
Open-Drain
Output
Slew-Rate
Control
VCC
Chip-Wide
Reset _{Input Register}
DQ
VCC
ENA
CLRN
Input Pin to
Core Delay (1)
VCCIO
Optional
PCI Clamp
Chip-Wide
Reset
40
Altera Corporation