EP20K200C Datasheet, PDF (48/90 Pages) Altera Corporation – Programmable Logic

APEX 20KC Programmable Logic Device Data Sheet
ClockLock & ClockBoost Timing Parameters
For the ClockLock and ClockBoost circuitry to function properly, the
incoming clock must meet certain requirements. If these specifications are
not met, the circuitry may not lock onto the incoming clock, which
generates an erroneous clock within the device. The clock generated by
the ClockLock and ClockBoost circuitry must also meet certain
specifications. If the incoming clock meets these requirements during
configuration, the APEX 20KC ClockLock and ClockBoost circuitry will
lock onto the clock during configuration. The circuit will be ready for use
immediately after configuration. In APEX 20KC devices, the clock input
standard is programmable, so the PLL cannot respond to the clock until
the device is configured. The PLL locks onto the input clock as soon as
configuration is complete. Figure 29 shows the incoming and generated
clock specifications.
1 For more information on ClockLock and ClockBoost circuitry,
see Application Note 115: Using the ClockLock and ClockBoost PLL
Features in APEX Devices.
Figure 29. Specifications for the Incoming & Generated Clocks
The t_I parameter refers to the nominal input clock period; the t_O parameter refers to the
nominal output clock period.
f _CLK1,f _CLK2,
f _CLK4
t _INDUTY
t _I + t _CLKDEV
Input
Clock
t _R (1) t _F (1)
t _OUTDUTY
t_O
t _I + t _INCLKSTB
ClockLock
Generated
Clock
t_O
t_O + t _JITTER t_O t _JITTER
Note to Figure 29:
(1) Rise and fall times are measured from 10% to 90%.
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