EP20K200C Datasheet, PDF (22/90 Pages) Altera Corporation – Programmable Logic

APEX 20KC Programmable Logic Device Data Sheet
Figure 11 shows the intersection of a row and column interconnect, and
how these forms of interconnects and LEs drive each other.
Figure 11. Driving the FastTrack Interconnect
Row Interconnect
MegaLAB Interconnect
LE
Column
Interconnect
Local
Interconnect
APEX 20KC devices include an enhanced interconnect structure for faster
routing of input signals with high fan-out. Column I/O pins can drive the
FastRow^TM interconnect, which routes signals directly into the local
interconnect without having to drive through the MegaLAB interconnect.
The FastRow lines traverse two MegaLAB structures. Also, these pins can
drive the local interconnect directly for fast setup times. On EP20K400C
and larger devices, the FastRow interconnect drives the two MegaLAB
structures in the top left corner, the two MegaLAB structures in the two
right corner, the two MegaLAB structures in the bottom left corner, and
the two MegaLAB structures in the bottom right corner. On EP20K200C
and smaller devices, FastRow interconnect drives the two MegaLAB
structures on the top and the two MegaLAB structures on the bottom of
the device. On all devices, the FastRow interconnect drives all local
interconnect in the appropriate MegaLAB structures except the end local
interconnect on the side of the MegaLAB opposite the ESB. Pins using the
FastRow interconnect achieve a faster set-up time, as the signal does not
need to use a MegaLAB interconnect line to reach the destination LE.
Figure 12 shows the FastRow interconnect.
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Altera Corporation