EP20K200C Datasheet, PDF (49/90 Pages) Altera Corporation – Programmable Logic

APEX 20KC Programmable Logic Device Data Sheet
Tables 11 and 12 summarize the ClockLock and ClockBoost parameters
for APEX 20KC devices.
Table 11. APEX 20KC ClockLock & ClockBoost Parameters Note (1)
Symbol
Parameter
t_R
t_F
t _INDUTY
t _INJITTER
Input rise time
Input fall time
Input duty cycle
Input jitter peak-to-peak
Condition
Min
40
t_OUTJITTER RMS jitter on ClockLock or
ClockBoost-generated clock
t_OUTDUTY Duty cycle for ClockLock or
45
ClockBoost-generated clock
t_LOCK (2)_, (3) Time required for ClockLock or
ClockBoost to acquire lock
Typ
Max
Unit
5
ns
5
ns
60
%
2% of input %
period
0.35% of %
output
period
55
%
40
µs
Table 12. APEX 20KC Clock Input & Output Parameters (Part 1 of 2) Note (1)
Symbol
Parameter
I/O Standard -7 Speed Grade -8 Speed Grade Units
Min Max Min Max
f_VCO (4)
Voltage controlled oscillator
operating range
200
500
200
500 MHz
f_CLOCK0
Clock0 PLL output frequency
for internal use
1.5
335
1.5
200 MHz
f_CLOCK1
Clock1 PLL output frequency
for internal use
20
335
20
200 MHz
f_{CLOCK0_EXT} Output clock frequency for
3.3-V LVTTL
(5)
(5)
(5)
(5) MHz
external clock0 output
2.5-V LVTTL
(5)
(5)
(5)
(5) MHz
1.8-V LVTTL
(5)
(5)
(5)
(5) MHz
GTL+
(5)
(5)
(5)
(5) MHz
SSTL-2 Class I (5)
(5)
(5)
(5) MHz
SSTL-2 Class II (5)
(5)
(5)
(5) MHz
SSTL-3 Class I (5)
(5)
(5)
(5) MHz
SSTL-3 Class II (5)
(5)
(5)
(5) MHz
LVDS
(5)
(5)
(5)
(5) MHz
Altera Corporation
49