EP20K200C Datasheet, PDF (11/90 Pages) Altera Corporation – Programmable Logic

APEX 20KC Programmable Logic Device Data Sheet
The LAB-wide control signals can be generated from the LAB local
interconnect, global signals, and dedicated clock pins. The inherent low
skew of the FastTrack interconnect enables it to be used for clock
distribution. Figure 4 shows the LAB control signal generation circuit.
Figure 4. LAB Control Signal Generation
Dedicated
4
Clocks
Global
4
Signals
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
SYNCLOAD
or LABCLKENA2
LABCLKENA1
LABCLR1 (1)
SYNCCLR
or LABCLK2 (2)
LABCLK1
LABCLR2 (1)
Notes to Figure 4:
(1) The LABCLR1 and LABCLR2 signals also control asynchronous load and asynchronous preset for LEs within the
LAB.
(2) The SYNCCLR signal can be generated by the local interconnect or global signals.
Logic Element
The LE, the smallest unit of logic in the APEX 20KC architecture, is
compact and provides efficient logic usage. Each LE contains a four-input
LUT, which is a function generator that can quickly implement any
function of four variables. In addition, each LE contains a programmable
register and carry and cascade chains. Each LE drives the local
interconnect, MegaLAB interconnect, and FastTrack interconnect routing
structures. See Figure 5.
Altera Corporation
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