EP20K200C Datasheet, PDF (72/90 Pages) Altera Corporation – Programmable Logic

APEX 20KC Programmable Logic Device Data Sheet
Table 42. APEX 20KC Selectable I/O Standard Input Adder Delays (Part 2 of 2) Note (1)
Symbol
LVDS
CTT
AGP
Parameter
Input adder delay for the LVDS I/O standard
Input adder delay for the CTT I/O standard
Input adder delay for the AGP I/O standard
Condition
Table 43. APEX 20KC Selectable I/O Standard Output Adder Delays Note (1)
Symbol
LVCMOS
LVTTL
2.5 V
1.8 V
PCI
GTl+
SSTL-3 Class I
SSTL-3 Class II
SSTL-2 Class I
SSTL-2 Class II
LVDS
CTT
AGP
Parameter
Condition
Output adder delay for the LVCMOS I/O standard
Output adder delay for the LVTTL I/O standard
Cload = 35 pF
Rup = 564.5 Ω
Rdn = 430 Ω (2)
Output adder delay for the 2.5-V I/O standard
Cload = 35 pF
Rup = 450 Ω
Rdn = 450 Ω (2)
Output adder delay for the 1.8-V I/O standard
Cload = 35 pF
Rup = 520 Ω
Rdn = 480 Ω (2)
Output adder delay for the PCI I/O standard
Cload = 10 pF
Rup = 1M Ω
Rdn = 25 Ω (2)
Output adder delay for the GTL+ I/O standard
Cload = 30 pF
Rup = 25 Ω (2)
Output adder delay for the SSTL-3 Class I I/O standard Cload1 = 0 pF
Cload2 = 30 pF
R = 25 Ω (2)
Output adder delay for the SSTL-3 Class II I/O standard Cload1 = 0 pF
Cload2 = 30 pF
R = 25 Ω (2)
Output adder delay for the SSTL-2 Class I I/O standard
Output adder delay for the SSTL-2 Class II I/O standard
Output adder delay for the LVDS I/O standard
Cload = 4 pF
R=100 Ω (2)
Output adder delay for the CTT I/O standard
Output adder delay for the AGP I/O standard
Note to Tables 42 and 43:
(1) These delays report the differences in delays for different I/O standards. Add the delay for the I/O standard that
is used to the external timing parameters.
(2) See Figure 36 for more information.
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Altera Corporation