EP20K200C Datasheet, PDF (24/90 Pages) Altera Corporation – Programmable Logic

APEX 20KC Programmable Logic Device Data Sheet
Table 8. APEX 20KC Routing Scheme
Source
Destination
Row Column LE
I/O Pin I/O Pin
Row I/O pin
Column I/O
pin
LE
ESB
Local
v
v
v
interconnect
MegaLAB
interconnect
Row
FastTrack
interconnect
Column
FastTrack
interconnect
FastRow
interconnect
ESB
Local
MegaLAB
Row
Column FastRow
Interconnect Interconnect FastTrack FastTrack Interconnect
Interconnect Interconnect
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
Product-Term Logic
The product-term portion of the MultiCore architecture is implemented
with the ESB. The ESB can be configured to act as a block of macrocells on
an ESB-by-ESB basis. Each ESB is fed by 32 inputs from the adjacent local
interconnect; therefore, it can be driven by the MegaLAB interconnect or
the adjacent LAB. Also, nine ESB macrocells feed back into the ESB
through the local interconnect for higher performance. Dedicated clock
pins, global signals, and additional inputs from the local interconnect
drive the ESB control signals.
In product-term mode, each ESB contains 16 macrocells. Each macrocell
consists of two product terms and a programmable register. Figure 13
shows the ESB in product-term mode.
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Altera Corporation