EP20K200C Datasheet, PDF (12/90 Pages) Altera Corporation – Programmable Logic

APEX 20KC Programmable Logic Device Data Sheet
Figure 5. APEX 20KC Logic Element
Carry-In
LAB-wide LAB-wide
Synchronous Synchronous
Load
Clear
Cascade-In
Register Bypass
Packed
Register Select
Programmable
Register
data1
data2
data3
data4
Look-Up
Table
(LUT)
Carry
Chain
Cascade
Chain
Synchronous
Load & Clear
Logic
labclr1
labclr2
Chip-Wide
Reset
labclk1
labclk2
labclkena1
labclkena2
Asynchronous
Clear/Preset/
Load Logic
Clock & Clock
Enable Select
Carry-Out
Cascade-Out
PRN
DQ
ENA
CLRN
To FastTrack Interconnect,
MegaLAB Interconnect,
or Local Interconnect
To FastTrack Interconnect,
MegaLAB Interconnect,
or Local Interconnect
Each LE’s programmable register can be configured for D, T, JK, or SR
operation. The register’s clock and clear control signals can be driven by
global signals, general-purpose I/O pins, or any internal logic. For
combinatorial functions, the register is bypassed and the output of the
LUT drives the outputs of the LE.
Each LE has two outputs that drive the local, MegaLAB, or FastTrack
interconnect routing structure. Each output can be driven independently
by the LUT’s or register’s output. For example, the LUT can drive one
output while the register drives the other output. This feature, called
register packing, improves device utilization because the register and the
LUT can be used for unrelated functions. The LE can also drive out
registered and unregistered versions of the LUT output.
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Altera Corporation