EP20K200C Datasheet, PDF (33/90 Pages) Altera Corporation – Programmable Logic

APEX 20KC Programmable Logic Device Data Sheet
Single-Port Mode
The APEX 20KC ESB also supports a single-port mode, which is used
when simultaneous reads and writes are not required. See Figure 22.
Figure 22. ESB in Single-Port Mode
Dedicated Inputs &
Global Signals
Dedicated Clocks
Note (1)
4
4
data[ ]
DQ
ENA
address[ ]
wren
outclken
inclken
inclock
outclock
DQ
ENA
DQ
ENA
Write
Pulse
Generator
RAM/ROM
128 × 16
256 × 8
Data In
512 × 4
1,024 × 2
2,048 × 1
Data Out
Address
DQ
ENA
To MegaLAB,
FastTrack &
Local
Interconnect
Write Enable
Note toFigure 22:
(1) All registers can be asynchronously cleared by ESB local interconnect signals, global signals, or the chip-wide reset.
Content-Addressable Memory
In APEX 20KC devices, the ESB can implement CAM. CAM can be
thought of as the inverse of RAM. When read, RAM outputs the data for
a given address. Conversely, CAM outputs an address for a given data
word. For example, if the data FA12 is stored in address 14, the CAM
outputs 14 when FA12 is driven into it.
Altera Corporation
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