AK7750 Datasheet, PDF (62/77 Pages) Asahi Kasei Microsystems – Audio DSP with Built-in Hands-Free Phone Features

[ASAHI KASEI]
[AK7750]
b) Offset RAM Write Preparation and Write ( under RUN condition )
This procedure is used to re-write Offset RAM (OFRAM) while a program is being executed. After inputting
a command code, data at up to 16 consecutive addresses to be re-written can be input . Next, input a write
command and a starting write address, and the re-write is executed whenever re-written address is
assigned. For example, this is how 5 writes are executed, starting at the Offset RAM address of “ 10 “:
Offset RAM execution address _{7 8 9 10 11 13 16 11 12 13 14 15}
ÈÈ
ÈÈÈ
write execution location
||Ç
|||
Be noted that address “ 13 “ is not processed until data at address “ 12 “ is re-written.
Data transfer procedure
* Write preparation
c Command code 98h (1 0 0 1 1 0 0 0)
d Data (0 0 0 0 0 0 0 0)
e Data (0 0 0 D12 y y y D8)
f Data (D12 y y y y y y D8)
* Write operation
c Command code 94h (1 0 0 1 0 1 0 0)
d Address MSB (0 0 A5 y y y y A0)
Note) Be sure to follow the procedure of write preparation first, then write. An erroneous operation occurs
if write is done without write preparation. “L” period of RDY for the write preparation is shorter than 1
master clock (20ns) under typical condition
S_RESET =H
RQ
SCLK
SI
RDY
SO
10011000 00 D12yD0
10010100 00 A5yyA0
AL
max 200ns
Longer of (16-n) x 2 MCLK
(n: number of data) and AL
RDYLG *)
*) RDYLG pulse width is 2 LRCLK clock time maximum if a program is so written to
surely re-write a new address within a single sampling time. After this, RDY signal
rises to high.
ORAM Write Preparation and Write
[MS0296-E-00]
62
2005/03