AK7750 Datasheet, PDF (19/77 Pages) Asahi Kasei Microsystems – Audio DSP with Built-in Hands-Free Phone Features

[ASAHI KASEI]
[AK7750]
2) Reset
(AVDD=DVDD=3.0 to 3.6V,Ta=-40°C to 85°C)
Parameter
Symbol
min
INIT_RESET
note 1) ^tRST
400
typ
max
Units
ns
CK_RESET
tRST
400
ns
S_RESET
tRST
400
ns
note1) At the power-on, it is OK to keep this pin to “L”. “H” transition must be made after the power-on and
master clock is full running.
3) Audio Interface
(AVDD=DVDD=3.0 to 3.6V,Ta= Ta=-40°C to 85°C, CL=20pF)
Parameter
Symbol
min
typ
Slave mode
BITCLK frequency
fBCLK
48
64
Delay time from BITCLK"↑“ to LRCLK note1) tBLRD
40
Delay time from LRCLK to BITCLK"↑" note1)
tLRBD
40
Delay time from LRCLK to serial data output
tLRD
Delay time from BITCLK to serial data output
tBSOD
Serial data input latch hold time
tBSIDS
40
Serial data input latch setup time
tBSIDH
40
Master mode
BITCLK frequency
fBCLK
64
BITCLK duty factor
50
Delay time from BITCLK"↑" to LRCLK note1)
tBLRD
40
Delay time from LRCLK to BITCLK"↑" note1)
tLRBD
40
Delay time from LRCLK to serial data output
tLRD
Delay time from BITCLK to serial data output
tBSOD
Serial data input latch hold time
tBSIDS
40
Serial data input latch setup time
tBSIDH
40
PCM Interface mode (SF/LF)
LRCLK frequency
fLRCK
8
BITCLK frequency
fBCLK
64
BITCLK duty factor
50
Delay time from BITCLK"↑" to LRCLK note1)
tBLRD
40
Delay time from LRCLK to BITCLK"↓" note1)
tLRBD
40
Delay time from LRCLK to serial data output
tLRD
Delay time from BITCLK to serial data output
tBSOD
Serial data input latch hold time
tBSIDS
40
Serial data input latch setup time
tBSIDH
40
LRCLK high level width (SF)
tLCKKH
64
LRCLK high level width (LF)
LRCLK low level width (LF)
tLCLKH
tLCLKL
300
1200
max
64
80
80
80
80
48
80
80
Units
fs
ns
ns
ns
ns
ns
ns
fs
%
ns
ns
ns
ns
ns
ns
kHz
fs
%
ns
ns
ns
ns
ns
ns
fs
ns
ns
Note 1) this value is specified such that LRCLK edge and rising edge of BITCLK never overlap
[MS0296-E-00]
19
2005/03