AK7750 Datasheet, PDF (31/77 Pages) Asahi Kasei Microsystems – Audio DSP with Built-in Hands-Free Phone Features

[ASAHI KASEI]
[AK7750]
„ Modes vs. PLL Relation
a) XTI Selection at CKSX = “H”
In the AK7750, the internal master clock MCLK usually runs at 36.864 MHz max. as shown below.
XTI mode0
XTI mode1
XTImode2
XTImode3
XTI
12.288MHz/11.2896MHz
XTI
18.432MHz/16.9344MHZ
XTI
Divider
&
PLL
MCLK
24.576MHz/22.5792MHz
36.864MHz/33.8688MHz
XTI
MCLK
36.864MHz/33.8688MHz 36.864MHz/33.8688MHz
Figure Mode Set vs. MCLK (internal master clock) relation
b) BITCLK( _I) Selection at CKSX = “L” ( @SMODE = “L” )
In the AK7750, the internal master clock MCLK usually runs at 38.864 MHz max. as shown below.
BCK mode0 _{BITCLK I}
3.072MHz/2.8224MHz
(fs=48kHz/44.1kHz only)
BCK mode1
BCK mode2
BITCLK I
6.144MHz/5.6448MHz
(fs=96kHz/88.2kHz only)
BITCLK I
(fs=192kHz/172.4kHz only)
12.288MHz/11.2896MHz
Divider
&
PLL
MCLK
36.864MHz/33.8688MHz
Figure Mode Set vs. MCLK ( internal master clock ) relation
[MS0296-E-00]
31
2005/03