AK7750 Datasheet, PDF (50/77 Pages) Asahi Kasei Microsystems – Audio DSP with Built-in Hands-Free Phone Features

[ASAHI KASEI]
[AK7750]
1) Write during reset phase
a) Control register write (during reset phase)
The data consists of 2 bytes used to perform control register write operations (during reset phase). When
all data has been entered, the new data is stored in the register at the rising edge of the 16^th count of
SCLK.
Data transfer procedure
c Command code
d Control data
60h, 62h, 64h, 68h, 6Ah, 6Ch, B8h
(D7 D6 D5 D4 D3 D2 D1 D0)
note) 40h, 44h and 48h are for testing and cannot be used.
For the function of each bit, see the description of Control registers, (section 2).
S_RESET
RQ
SCLK
SI
SO
60h
D7 ***D1 D0
64h
D7 ***D1 D0
Note) It must be set always 0 to D0.
Control Registers write operation
[MS0296-E-00]
50
2005/03