AK7750 Datasheet, PDF (12/77 Pages) Asahi Kasei Microsystems – Audio DSP with Built-in Hands-Free Phone Features

[ASAHI KASEI]
[AK7750]
Pin Pin Name
NO.
46 CKS1
47 CKS0
48 TESTI1
49 LFLT
50 AVDD
51 AVSS
52 AVSS
53 AOUTR
54 AOUTL
55 AVDD
56 AVDD
57 VREFH
58 VCOM
59 VREFL
60 AVSS
61 AINR-
62 AINR+
63 AINL-
64 AINL+
I/O
Function
Pin Classification
I Master Clock Set pin (pulled-down)
Control
I Master Clock Set pin (pulled-down)
I Test pin (pulled-down)
Test
Tie this pin to DVSS.
- PLL RC component connect pin
Analog Block
A serially connected resistor (R=22kΩ) and capacitor
(C=1.5nF) pair is connected to this pin (when PLL is not used
at all, tie this pin to AVSS).
- Analog Power Supply pin 3.3 V ( typ ).
- Analog Ground pin 0 V (silicon substrate potential)
- Analog Ground pin 0 V (silicon substrate potential)
O DAC R-ch Analog Output pin
O DAC L-ch Analog Output pin
- Analog Power Supply pin 3.3 V (typ).
- Analog Power Supply pin 3.3 V (typ).
I Analog Reference Voltage Input pin
This pin is normally tied to AVDD. Connect Capacitors of 0.1
uF and 10 uF between this pin and VSS.
O Analog Common Voltage Output pin
Connect Capacitors of 0.1 uF and 10 uF between this pin and
VSS. No external circuits should be connected to this pin.
I Analog Reference Voltage Input pin
Tie this pin to AVSS for normal operation.
- Analog Ground pin 0 V (silicon substrate potential)
I ADC R-ch Analog Inverted Input pin
I ADC R-ch Analog Non-Inverted Input pin
I ADC L-ch Analog Inverted Input pin
I ADC L-ch Analog Non-Inverted Input pin
Note) Digital input pins should not be kept open, except for pulled-down pins and BITCLK-I and LRCLK-I
(EESEL=”L”) pins in master mode (pulled-down pins are kept open or connected to DVSS when they are
not used).
[MS0296-E-00]
12
2005/03