AK7750 Datasheet, PDF (43/77 Pages) Asahi Kasei Microsystems – Audio DSP with Built-in Hands-Free Phone Features

[ASAHI KASEI]
[AK7750]
(3) Power-ON Sequence
Power-On while holding INIT_RESET = “L” and S_RESET = “L”.
Control registers are initialized during INIT_RESET = “L” ( see note 1 and note 2 ).
After power is applied, INIT_RESET = “H” and REF generating circuit ( Analog Reference Voltage
source ) and PLL are turned on, and master clock is generated by the PLL.
Communication with the AK7750 should be made after the PLL oscillation is stabilized (50ms@ XTI mode,
and BCK mode 0/1/2; 175ms@BCK mode 3).
An initialization by INIT_RESET is usually required only for power- on.
The power should be turned on when CK_RESET pin is linked with INIT_RESET or while it is fixed to
“H”.
Note1) to assure proper initialization, it is necessary that power is turned on and then the master clock
(XTI) is supplied.
Note2) when a crystal oscillator is used, INIT_RESET should be set to “H” after the oscillation is
stabilized. Stabilization time of the oscillation varies depending upon types of crystal oscillators and
external circuits used.
Note) Do not stop the system clocks (Slave Mode: XTI, LRCLK, BITCLK and Master Mode : XTI ) except
during the initial reset ( INIT_RESET = “L” and S_RESET = “L” ) or at a system reset ( S_RESET = “L” )
or at a Clock reset ( CK_RESET = “L” ).
If these clocks are not applied, there is a possibility that an excess current will flow, causing erratic
operation.
AVDD
DVDD
INIT_RESET
( CK_RESET )
S_RESET
XTI
(internal PLLCLK)
CLKO
Power Off
INIT_RESET =”H”
after crystal startup
PLL startup time
command code
Inhibit of command loading of DSP program
50 ms@ XTI mode
(no time-constraint)
50ms@BCK mode 0/1/2
175ms@BCK mode 3
start CLKO output
Figure Power-up Sequence
[MS0296-E-00]
43
2005/03