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AK7750 Datasheet, PDF (36/77 Pages) Asahi Kasei Microsystems – Audio DSP with Built-in Hands-Free Phone Features
[ASAHI KASEI]
[AK7750]
2) CONT1: RAM control
This register should be changed only during a system reset ( S_RESET =”L”).
Command Code Name
D7
D6
D5
D4
D3
D2
D1
Write Read
62h
72h
CONT1 DATARAM
RM
BANK1 BANK0 CMP_N
SS1
SS0
D0 Default
X
0000_000x
c D7:DATARAM DATARAM addressing mode selector
0: Ring addressing mode
1: Linear addressing mode
DATARAM is 256-words x 24-bits and has 2 addressing pointers (DP0, DP1).
Ring addressing mode: The starting address increments by 1 every sample period.
Linear addressing mode: The starting address is always the same, DP0 = 00h and DP1 = 80h.
d D6:RM: Decompress bit mode
0: SIGN bit
1: Random data
When either Data Compression or Data Expansion mode is selected (CMP-N (D3) = “0”), data for the
lower bits where no data exists at the data expansion is selectable. When it is “0”, the sign bit is filled
in and when it is “0”, the M-series random number is filled in.
e D5,D4:BANK[1:0] DLRAM Setting
Mode BANK1
BANK0
Memory
0
0
0
24bit 1kword(RAM A)
1
0
1
16bit 2kword(RAM A),24bit 1kword(RAM B)
2
1
0
24bit 1kword(RAM A),16bit 2kword(RAM B)
3
1
1
16bit 4kword(RAM A)
note) When a hands-free function is used, set the DLRAM at mode0, which allocates the memory for
hands-free processing.
At DLRAM mode3, both Pointers 0 & 1 can be used. With DLRAM modes0, 1 and 2, Pointer 0 is
allocated to RAM A and Pointer 1 is allocated to RAM B.
f D3:CMP_N 16bitDLRAM Compress & Decompress selector
When mode 1,2 or 3 is selected, this register can turn ON or OFF the compress/decompress function.
0 : Compression / Expansion ON
1 : Compression / Expansion OFF
When both compression and expansion are enabled (ON), the upper 23 bit data on DBUS is
compressed to 15 bit data and it is written into DLRAM.
In read mode, the 15 bit data is expanded and the resulting data is output on DBUS.
Lower bit setting during data expansion follows as is set by D6 : RM.
With this data compression, 23 bit equivalent Dynamic Range and 15 bit equivalent S/N + D are
obtained.
When both compression and expansion are disabled (OFF), the upper 16 bit data on DBUS is directly
written into or read out of DLRAM. During the read operation, the lower 16 bit returns to DBUS a value
of 0000h.
g D2,D1:SS[1:0] DLRAM setting of sampling timing (only for RAM A)
Mode
SS1
SS0 RAM A mode selected by BANK[1:0]
0
0
0
Update every sampling time
1
0
1
Update every 2 sampling time
2
1
0
Update every 4 sampling time
3
1
1
Update every 8 sampling time
Note) When modes 1,2 or 3 are selected, aliasing will occur.
h D0: set to “0”
Note) Underlines “_” mean default setting.
[MS0296-E-00]
36
2005/03