AK7750 Datasheet, PDF (30/77 Pages) Asahi Kasei Microsystems – Audio DSP with Built-in Hands-Free Phone Features

[ASAHI KASEI]
[AK7750]
b) BITCLK(_I) Selection at CKSX = “L” (`SMODE=”L”)
BCK Modes 0,1,2 are used when bit clock ( BITCLK_I,BITCLK ) is used instead of XTI. A clock fed on the
BITCLK-I pin is directly frequency-multiplied by the PLL and a master clock (MCLK) is generated.
XTI
0
Divider
1
XTO
BITCLK_I
0
C l o c ^BITCLK
1
EESEL
SMODE
CKSX
PLL
MCLK
BITCLK
AK7750
Internal connection image diagram
Input on BITCLK(_I) pin a divided-by-64 clock of the LRCLK(_I) ( 64fs ).
( BITCLK( _I) must be in synchronized with LRCLK (_I)).
LRCLK_I
LRCLK
Left ch
R ight ch
B ITC LK _I
B ITC LK
32×B IT C LK _I(B IT C LK )
32×B IT C LK _I(B IT C LK )
Figure BITCLK ( -I ) and LRCLK ( -I ) relation ( BITCLK ( -I ) = LRCLK ( -I ) / 64 )
[MS0296-E-00]
30
2005/03